
//段落必须用##包围,注释用/开头

//配置段，只有变量配置，
#CONFIG_SETTING#

//变量名称=变量值，等号中间不要有空格
//选择要测试的内存块，0-低16位，1-高16位，2-全32位，默认为全测
DEVICE_SELECT=2
//0:same add; 1:different add
CALIBRATION_METHOD=0

//1:four loop scan calibration
SCAN_MODE=0

//initial register setting，after this, clock calibration and 90 degree DLL calibration
#INIT_REGS#

/* DDR_CLOCK_225M */
//0xbff70088=0x4fe120d
//0xbfedc050=2
//sleep unit is millisecond
//sleep=1
//0xbfedc050=0
//sleep=2

/* 1. config device */

/* 1G bit one chip * 2 */
0xbfd70034=0x1430000
/* config timing and PHY, time_para0, time_para1 and time_para2 */
0xbfd70024=0x1040f05
0xbfd70028=0x2b000304
0xbfd7002c=0x14020513

/* 2. set dram_ctrl */

/* dram_ctrl0 ~ dram_ctrl1 */
0xbfd70038=0x72120001

/* 3. ddr clock calibration (HW) */

/* Configure ddrclk_dly_window (0xbfd7_00a4[2:0]), low_freq_ddr (0xbfd7_00a4[8]) and dly90_dly_window (0xbfd7_00a4[5:4]) */
0xbfd700a4=0xf000
0xbfd70048=0x10000010

/* dly_ddrclk0_para, dly_ddrclkn0_para, dly_ddrclk1_para, dly_ddrclkn1_para: (0xbfd7_00a0, bit[31:16], initial=0) */
0xbfd700a0=0


/* 4. Delay 90 degree DLL calibration */

//config register setting, after this, READ operation and Calibrate
#CONFIG_REGS#

/* 5. Configure Output Drivers */
//0xbfd700a0=0x550000

//Achilles201203222005_EtronTech
//Condition: Device_ODT=75ohm, Controller_ODT=50ohm
0xbfd70054=0x03030303
//0xbfd70054=0x08080808
0xbfd700ac=0x02020202
0xbfd700b0=0x00000202
0xbfd700b4=0x01010000
//Achilles accroding to the waveform
0xbfd700a0=0x33990000
//0xbfd700a0=0x00ff0000
0xbfd700b8=0x00000707
0xbfd700a8=0x77220077
0xbfd700bc=0x74017294
//Achilles201203222005
// modify DDR_CLK DLL calib result 
0xbfd70040=0x120
//Lynn: READ-WRITE 
0xbfd70028=0x2b020504

sleep=1

/* 6. DDR2 Device Initialization Sequence */
0xbfd70018=0
/* delay minimum 400ns, then PRECHARGE ALL */
sleep=1
0xbfd70000=1

/* issue LOAD MODE to EMR(2) */
0xbfd70020=0x8000
0xbfd70004=1

/* issue LOAD MODE to EMR(3) */
0xbfd70020=0xC000
0xbfd70004=1

/* issue LOAD MODE to EMR to enable DLL */
0xbfd70020=0x4000
0xbfd70004=1
sleep=1

/* issue PRECHARGE ALL */
0xbfd70000=1

/* issue REFRESH twice */
0xbfd70008=1
0xbfd70008=1

/* issue LOAD MODE to MR with LOW to A8 to initialize device operation */
0xbfd70020=0xa62
0xbfd70004=1

/* issue LOAD MODE to EMR to enable OCD default by setting bits E7, E8, E9 to 1 */
/* 50 ohm */
//0xbfd70020=0x43c4
/* 150 ohm */
//0xbfd70020=0x43c0
/* 75 ohm */
0xbfd70020=0x4384

0xbfd70004=1

/* 50 ohm */
//0xbfd70020=0x4044
/* 150 ohm */
//0xbfd70020=0x4040
/* 75 ohm */
0xbfd70020=0x4004

0xbfd70004=1

/* inform the DDR2 controller that the initialization is finished */
0xbfd70018=1

/* 7. Configure registers for WRITE operation */